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LTC1746 Low Power,14-Bit, 25Msps ADC
FEATURES
s s s s s s s s s
DESCRIPTIO
Sample Rate: 25Msps 77.5dB SNR and 91dB SFDR (3.2V Range) 74dB SNR and 96dB SFDR (2V Range) No Missing Codes Single 5V Supply Low Power Dissipation: 390mW Selectable Input Ranges: 1V or 1.6V 240MHz Full Power Bandwidth S/H Pin Compatible Family 25 Msps: LTC1746 (14-Bit), LTC1745 (12-Bit) 50 Msps: LTC1744 (14-Bit), LTC1743 (12-Bit) 65 Msps: LTC1742 (14-Bit), LTC1741 (12-Bit) 80 Msps: LTC1748 (14-Bit), LTC1747 (12-Bit)
The LTC (R)1746 is a 25Msps, sampling 14-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. Pin selectable input ranges of 1V and 1.6V along with a resistor programmable mode allow the LTC1746's input range to be optimized for a wide variety of applications. The LTC1746 is perfect for demanding communications applications with AC performance that includes 77.5dB SNR and 91dB spurious free dynamic range. Ultralow jitter of 0.3psRMS allows undersampling with excellent noise performance. DC specs include 3LSB INL maximum and no missing codes over temperature. The digital interface is compatible with 5V, 3V and 2V logic systems. The ENC and ENC inputs may be driven differentially from PECL, GTL and other low swing logic families or from single-ended TTL or CMOS. The low noise, high gain ENC and ENC inputs may also be driven by a sinusoidal signal without degrading performance. A separate digital output power supply can be operated from 0.5V to 5V, making it easy to connect directly to low voltage DSPs or FIFOs. The TSSOP package with a flow-through pinout simplifies the board layout.
APPLICATIO S
s s s s s s
Telecommunications Medical Imaging Receivers Base Stations Spectrum Analysis Imaging Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
BLOCK DIAGRA
AIN+ 1V DIFFERENTIAL ANALOG INPUT
25Msps, 14-Bit ADC with a 1V Differential Input Range
OVDD OF D13 D0 CLKOUT 0.1F 0.5V TO 5V 0.1F
AIN-
S/H AMP
14-BIT PIPELINED ADC
14
SENSE BUFFER
RANGE SELECT
DIFF AMP GND CONTROL LOGIC
1746 BD
VCM 4.7F
2.35VREF
REFLB 0.1F 1F
REFHA 4.7F
REFLA
REFHB
ENC
ENC
MSBINV
0.1F 1F
DIFFERENTIAL ENCODE INPUT
U
OUTPUT LATCHES * * * OGND VDD 1F 1F 5V 1F OE
W
U
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1
LTC1746
ABSOLUTE MAXIMUM RATINGS
OVDD = VDD (Notes 1, 2)
PACKAGE/ORDER INFORMATION
TOP VIEW SENSE VCM GND AIN+ AIN- GND VDD VDD GND REFLB REFHA GND GND REFLA REFHB GND VDD VDD GND VDD GND MSBINV ENC ENC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FW PACKAGE 48-LEAD PLASTIC TSSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 OF OGND D13 D12 D11 OVDD D10 D9 D8 D7 OGND GND GND D6 D5 D4 OVDD D3 D2 D1 D0 OGND CLKOUT OE
Supply Voltage (VDD) ............................................. 5.5V Analog Input Voltage (Note 3) .... - 0.3V to (VDD + 0.3V) Digital Input Voltage (Note 4) ..... - 0.3V to (VDD + 0.3V) Digital Output Voltage ................. - 0.3V to (VDD + 0.3V) OGND Voltage ..............................................- 0.3V to 1V Power Dissipation ............................................ 2000mW Operating Temperature Range LTC1746C ............................................... 0C to 70C LTC1746I ............................................ - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1746CFW LTC1746IFW
TJMAX = 150C, JA = 35C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
CO VERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Full-Scale Tempco
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS
q
MIN 14 -3 -1 - 30 - 2.5
q q
TYP 1 0.5 5 1 40
MAX 3 1 30 2.5
UNITS Bits LSB LSB mV %FS ppm/C
(Note 6) (Note 7) External Reference (SENSE = 1.6V) IOUT(REF) = 0
q q
A ALOG I PUT
SYMBOL VIN IIN CIN tACQ tAP tJITTER CMRR PARAMETER
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS 4.75V VDD 5.25V Sample Mode ENC < ENC Hold Mode ENC > ENC
q q q
MIN -1
TYP 1 to 1.6
MAX 1
UNITS V A pF pF
Analog Input Range (Note 8) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio
8 4 15 0 0.3 18
psRMS dB
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1.0V < (AIN = AIN
-
+) < 3.5V
80
2
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W
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WW
W
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ns ns
LTC1746
DY A IC ACCURACY
SYMBOL SNR PARAMETER Signal-to-Noise Ratio
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 5)
CONDITIONS 5MHz Input Signal (2V Range) 5MHz Input Signal (3.2V Range) 30MHz Input Signal (2V Range) 30MHz Input Signal (3.2V Range) 70MHz Input Signal (2V Range) 70MHz Input Signal (3.2V Range) SFDR Spurious Free Dynamic Range 5MHz Input Signal (2V Range) 5MHz Input Signal (3.2V Range) 30MHz Input Signal (2V Range) 30MHz Input Signal (3.2V Range) 70MHz Input Signal (2V Range) 70MHz Input Signal (3.2V Range) S/(N + D) Signal-to-(Noise + Distortion) Ratio 5MHz Input Signal (2V Range) 5MHz Input Signal (3.2V Range) 30MHz Input Signal (2V Range) 30MHz Input Signal (3.2V Range) 70MHz Input Signal (2V Range) 70MHz Input Signal (3.2V Range) THD Total Harmonic Distortion 5MHz Input Signal, First 5 Harmonics (2V Range) 5MHz Input Signal, First 5 Harmonics (3.2V Range) 30MHz Input Signal, First 5 Harmonics (2V Range) 30MHz Input Signal, First 5 Harmonics (3.2V Range) 70MHz Input Signal, First 5 Harmonics (2V Range) 70MHz Input Signal, First 5 Harmonics (3.2V Range) IMD Intermodulation Distortion Sample-and-Hold Bandwidth fIN1 = 4MHz, fIN2 = 5.1MHz (2V Range) fIN1 = 4MHz, fIN2 = 5.1MHz (3.2V Range) RSOURCE = 50
q q q
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance CONDITIONS IOUT = 0 IOUT = 0 4.75V VDD 5.25V 1mA IOUT 1mA
U
WU U
MIN 75.5
TYP 74 77.5 73.5 76.5 72.5 75
MAX
UNITS dBFS dBFS dBFS dBFS dBFS dBFS dB dB dB dB dB dB dBFS dBFS dBFS dBFS dBFS dBFS dB dB dB dB dB dB dBc dBc MHz
80
96 91 95 86.5 79 71
75
74 77.5 73.5 76.5 71.5 70 - 92 - 90 - 90.5 - 85.5 -77.5 -70 86 84 240
U
(Note 5)
MIN 2.29 TYP 2.35 30 3 4 MAX 2.41 UNITS V ppm/C mV/V
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LTC1746 DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage D13 to D0 Hi-Z Output Capacitance D13 to D0 Output Source Current Output Sink Current CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD MSBINV and OE Only OVDD = 4.75V OVDD = 4.75V VOUT = 0V to VDD, OE = High OE = High (Note 8) VOUT = 0V VOUT = 5V IO = -10A IO = - 200A IO = 160A IO = 1.6mA
q q q q q q q
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
MIN 2.4 0.8 10 1.5 4.74 4 0.05 0.1 0.4 10 15 - 50 50 TYP MAX UNITS V V A pF V V V V A pF mA mA
POWER REQUIRE E TS
SYMBOL VDD IDD PDIS OVDD PARAMETER Positive Supply Voltage Positive Supply Current Power Dissipation Digital Output Supply Voltage
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS 2V Range, Full-Scale Input 2V Range, Full-Scale Input
q q
TI I G CHARACTERISTICS
SYMBOL fSAMPLE t1 t2 t3 t4 t5 t6 t7 t8 PARAMETER Sampling Frequency ENC Low Time ENC High Time Aperture Delay of Sample-and-Hold ENC to Data Delay ENC to CLKOUT Delay CLKOUT to Data Delay DATA Access Time After OE BUS Relinquish Time Data Latency
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS (Note 9) (Note 9) (Note 9) (Note 8) CL = 10pF (Note 8) CL = 10pF (Note 8) CL = 10pF (Note 8) CL = 10pF (Note 8) (Note 8)
q q q q q q
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with GND (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND, they will be clamped by internal diodes. This product can handle input currents of >100mA below GND without latchup. These pins are not clamped to VDD.
4
UW
U
U
MIN 4.75
TYP 78 390
MAX 5.25 93 465 VDD
UNITS V mA mW V
0.5
UW
MIN 1 19 19 1.4 0.5 0
TYP 20 20 0 4 2 2 10 10 5
MAX 25 1000 1000 10 5 25 25
UNITS MHz ns ns ns ns ns ns ns ns cycles
Note 5: VDD = 5V, fSAMPLE = 25MHz, differential ENC/ENC = 2VP-P 25MHz sine wave, input range = 1.6V differential, unless otherwise specified. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Bipolar offset is the offset voltage measured from - 0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111. Note 8: Guaranteed by design, not subject to test. Note 9: Recommended operating conditions.
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LTC1746 TYPICAL PERFOR A CE CHARACTERISTICS
Typical INL
1.0 1.0
0.5
DNL ERROR (LSB)
INL ERROR (LSB)
AMPLITUDE (dB)
0
-0.5
-1.0 0 4000 8000 CODE 12000 16000
1746 G01
Nonaveraged, 32768 Point FFT, Input Frequency = 5MHz, 2V Range
0 -10 -20 -30
AMPLITUDE (dB) AMPLITUDE (dB)
-50 -60 -70 -80 -90 -100 -110 -120 0 2 4 8 6 FREQUENCY (MHz) 10 12
1746 G04
-50 -60 -70 -80 -90 -100 -110 -120 0 2 4 8 6 FREQUENCY (MHz) 10 12
1746 G05
AMPLITUDE (dB)
-40
Nonaveraged, 32768 Point FFT, Input Frequency = 70MHz, 2V Range
0 -10 -20 -30 AMPLITUDE (dB) AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110 -120 0 2 4 8 6 FREQUENCY (MHz) 10 12
1746 G07
-50 -60 -70 -80 -90 -100 -110 -120 0 2 4 8 6 FREQUENCY (MHz) 10 12
1746 G08
AMPLITUDE (dB)
UW
Typical DNL
0 -10 -20
Nonaveraged, 32768 Point FFT, Input Frequency = 5MHz, 3.2V Range
0.5
-30 -40 -50 -60 -70 -80 -90 -100 -110
0
-0.5
-1.0 0 4000 8000 CODE 12000 16000
1746 G02
-120 0 2 4 8 6 FREQUENCY (MHz) 10 12
1746 G03
Nonaveraged, 32768 Point FFT, Input Frequency = 30MHz, 3.2V Range
0 -10 -20 -30 -40
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
Nonaveraged, 32768 Point FFT, Input Frequency = 30MHz, 2V Range
0
2
4 8 6 FREQUENCY (MHz)
10
12
1746 G06
Nonaveraged, 32768 Point 2-Tone FFT, Input Frequency = 4MHz and 5.1MHz, 3.2V Range
0 -10 -20 -30 -40 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
Nonaveraged, 32768 Point 2-Tone FFT, Input Frequency = 4MHz and 5.1MHz, 2V Range
0
2
4 8 6 FREQUENCY (MHz)
10
12
1746 G09
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LTC1746 TYPICAL PERFOR A CE CHARACTERISTICS
Grounded Input Histogram
25000 78 77 20000 76 75 74 90 2V RANGE SFDR (dB) 80 70 60 50 SNR (dBFS) 73 72 71 70 69 5000 68 67 0 8167 8168 8169 8170 CODE 8171 8172
1746 G10
COUNT
15000
10000
SNR vs Input Frequency and Amplitude 3.2V Range
80 -1dBFS 75 -6dBFS 70 70
SNR (dB)
SNR (dB)
65 60 55 50 0 10 20 30 40 50 60 70 80 90 100 INPUT FREQUENCY (MHz)
1746 G13
SFDR vs Input Frequency and Amplitude, 3.2V Range
110 -20dBFS 100 90 SFDR (dBFS) -1dBFS 80 70 60 50 40 0 10 20 30 40 50 60 70 80 90 100 INPUT FREQUENCY (MHz)
1746 G15
SFDR (dBFS)
6
UW
SNR vs Sample Rate, Input Frequency = 5MHz, -1dB
110 3.2V RANGE 100
SFDR vs Sample Rate, Input Frequency = 5MHz, -1dB
2V RANGE 3.2V RANGE
66
0
10
20 30 40 SAMPLE RATE (Msps)
50
60
1746 G11
0
10
20 30 40 SAMPLE RATE (Msps)
50
60
1746 G12
SNR vs Input Frequency and Amplitude 2V Range
80 75
-1dBFS -6dBFS
65 60 55 50 0 10 20 30 40 50 60 70 80 90 100 INPUT FREQUENCY (MHz)
1746 G14
-20dBFS
-20dBFS
SFDR vs Input Frequency and Amplitude, 2V Range
110 -20dBFS 100
-6dBFS
90 -6dBFS 80 -1dBFS 70 60 50 40 0 50 150 100 INPUT FREQUENCY (MHz) 200
1746 G16
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LTC1746 TYPICAL PERFOR A CE CHARACTERISTICS
2nd and 3rd Harmonic vs Input Frequency, 3.2V Range, -1dB
-30 -30
-50 DISTORTION (dB) DISTORTION (dB)
-70 3RD HARMONIC -90 2ND HARMONIC -110
-70 3ND HARMONIC -90
DISTORTION (dB)
-130
0
10 20 30 40 50 60 70 80 90 100 INPUT FREQUENCY (MHz)
1746 G17
Worst Harmonic 4th or Higher vs Input Frequency, 2V Range, -1dB
-60
-70 SFDR (dBc AND dBFS) DISTORTION (dB)
-80
90
POWER (mW)
-90
-100
-110
0
50 150 100 INPUT FREQUENCY (MHz)
UW
1746 G20
2nd and 3rd Harmonic vs Input Frequency, 2V Range, -1dB
-60
Worst Harmonic 4th or Higher vs Input Frequency, 3.2V Range, -1dB
-50 2ND HARMONIC
-70
-80
-90
-110
-100
-130
0
50 150 100 INPUT FREQUENCY (MHz)
200
1746 G18
-110
0
10 20 30 40 50 60 70 80 90 100 INPUT FREQUENCY (MHz)
1746 G19
SFDR vs Input Amplitude, 2V Range, 5MHz Input Frequency
110
500 480
Power vs Sample Rate, Input Frequency = 5MHz
100 SFDR dBFS
460 440 420 400 380 360 340 320 3.2V RANGE 2V RANGE
80 SFDR dBc 70
200
60 -60
300
-20 -40 INPUT AMPLITUDE (dBFS)
0
1746 G21
0
10
30 40 20 SAMPLE RATE (Msps)
50
60
1746 G22
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LTC1746
PI FU CTIO S
SENSE (Pin 1): Reference Sense Pin. Ground selects 1V. VDD selects 1.6V. Greater than 1V and less than 1.6V applied to the SENSE pin selects an input range of VSENSE, 1.6V is the largest valid input range. VCM (Pin 2): 2.35V Output and Input Common Mode Bias. Bypass to ground with 4.7F ceramic chip capacitor. GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37): ADC Power Ground. AIN+ (Pin 4): Positive Differential Analog Input. AIN - (Pin 5): Negative Differential Analog Input. VDD (Pins 7, 8, 17, 18, 20): 5V Supply. Bypass to GND with 1F ceramic chip capacitor. REFLB (Pin 10): ADC Low Reference. Bypass to Pin 11 with 0.1F ceramic chip capacitor. Do not connect to Pin 14. REFHA (Pin 11): ADC High Reference. Bypass to Pin 10 with 0.1F ceramic chip capacitor, to Pin 14 with a 4.7F ceramic capacitor and to ground with 1F ceramic capacitor. REFLA (Pin 14): ADC Low Reference. Bypass to Pin 15 with 0.1F ceramic chip capacitor, to Pin 11 with a 4.7F ceramic capacitor and to ground with 1F ceramic capacitor. REFHB (Pin 15): ADC High Reference. Bypass to Pin 14 with 0.1F ceramic chip capacitor. Do not connect to Pin 11. MSBINV (Pin 22): MSB Inversion Control. Low inverts the MSB, 2's complement output format. High does not invert the MSB, offset binary output format. ENC (Pin 23): Encode Input. The input sample starts on the positive edge. ENC (Pin 24): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1F ceramic for single-ended encode signal. OE (Pin 25): Output Enable. Low enables outputs. Logic high makes outputs Hi-Z. CLKOUT (Pin 26): Data Valid Output. Latch data on the rising edge of CLKOUT. OGND (Pins 27, 38, 47): Output Driver Ground. D0-D3 (Pins 28 to 31): Digital Outputs. D0 is the LSB. OVDD (Pins 32, 43): Positive Supply for the Output Drivers. Bypass to ground with 0.1F ceramic chip capacitor. D4-D6 (Pins 33 to 35): Digital Outputs. D7-D10 (Pins 39 to 42): Digital Outputs. D11-D13 (Pins 44 to 46): Digital Outputs. D13 is the MSB. OF (Pin 48): Over/Under Flow Output. High when an over or under flow has occurred.
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LTC1746 TI I G DIAGRA W
N ANALOG INPUT t3 t2 t1 t4 DATA (N - 5) D11 TO D0 t5 CLKOUT t5 DATA (N - 4) D11 TO D0 DATA (N - 3) D11 TO D0 t8 DATA N D11 TO D0, OF AND CLKOUT
1746 TD
FU CTIO AL BLOCK DIAGRA
AIN+ 1V DIFFERENTIAL ANALOG INPUT S/H AMP 14-BIT PIPELINED ADC 14 OUTPUT LATCHES * * *
AIN-
SENSE BUFFER
RANGE SELECT
DIFF AMP GND CONTROL LOGIC
1746 BD
VCM 4.7F
2.35VREF
0.1F 1F 1F
W
U
UW
ENCODE t6 DATA
t7 OE
DATA
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OVDD OF D13 D0 CLKOUT 0.1F 0.5V TO 5V 0.1F
OGND
VDD 1F 1F
5V 1F
REFLB
REFHA 4.7F
REFLA
REFHB
ENC
ENC
MSBINV
OE
0.1F
DIFFERENTIAL ENCODE INPUT
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LTC1746
APPLICATIO S I FOR ATIO
DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S / (N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:
THD = 20Log V22 + V32 + V 42 + ...Vn2 V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.
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If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa - fb and 2fb - fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when a rising ENC equals the ENC voltage to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = - 20log (2) * FIN * TJITTER
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LTC1746
APPLICATIO S I FOR ATIO
CONVERTER OPERATION
As shown in Figure 1, the LTC1746 is a CMOS pipelined multistep converter. The converter has four pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later, see the Timing Diagram section. The analog input is differential for improved common mode noise immunity and to maximize the input range. Additionally, the differential input drive will reduce even order harmonics of the sample-and-hold circuit. The encode input is also differential for improved common mode noise immunity. The LTC1746 has two phases of operation, determined by the state of the differential ENC/ENC input pins. For
AIN+
-
FIRST STAGE INPUT S/H 5-BIT PIPELINED ADC STAGE
AIN
VCM 4.7F
2.35V REFERENCE SHIFT REGISTER AND CORRECTION RANGE SELECT INTERNAL REFERENCES TO ADC INTERNAL CLOCK SIGNALS
SENSE
REF BUF DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER
DIFF REF AMP
REFLB 0.1F 1F
REFHA 4.7F
Figure 1. Functional Block Diagram
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brevity, the text will refer to ENC greater than ENC as ENC high and ENC less than ENC as ENC low. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and visa versa.
SECOND STAGE 4-BIT PIPELINED ADC STAGE THIRD STAGE 4-BIT PIPELINED ADC STAGE FOURTH STAGE 4-BIT FLASH ADC OVDD 0.5V TO 5V OF CONTROL LOGIC OUTPUT DRIVERS D13 * * * D0 CLKOUT
1746 F01
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REFLA
REFHB
ENC
ENC
MSBINV
OE
OGND
0.1F 1F
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LTC1746
APPLICATIO S I FOR ATIO
When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the "Input S/H" shown in the block diagram. At the instant that ENC transitions from low to high, the sampled input is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third stage, resulting in a third stage residue that is sent to the fourth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally delayed such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample Hold Operation Figure 2 shows an equivalent circuit for the LTC1746 CMOS differential sample-and-hold. The differential analog inputs are sampled directly onto sampling capacitors (CSAMPLE) through CMOS transmission gates. This direct capacitor sampling results in the lowest possible noise for a given sampling capacitor size. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when ENC/ENC is low, the transmission gate connects the analog inputs to the sampling capacitors, and they charge to and track the differential input voltage. When ENC/ENC transitions from low to high the sampled input voltage is held on the sampling capacitors. During the hold phase when ENC/ENC is high the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC/ENC transitions from high to low the inputs are reconnected to the sampling capacitors to
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acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Common Mode Bias The ADC sample-and-hold circuit requires differential drive to achieve specified performance. Each input should swing 0.8V for the 3.2V range or 0.5V for the 2V range, around a common mode voltage of 2.35V. The VCM output pin (Pin 2) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with 4.7F or greater capacitor.
LTC1746 VDD CSAMPLE 4pF CPARASITIC 4pF VDD AIN+ CSAMPLE 4pF CPARASITIC 4pF 5V AIN- BIAS 2V 6k ENC ENC 6k 2V
1746 F02
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Figure 2. Equivalent Input Circuit
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LTC1746
APPLICATIO S I FOR ATIO
Input Drive Impedance
As with all high performance, high speed ADCs the dynamic performance of the LTC1746 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of encode the sampleand-hold circuit will connect the 4pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when encode rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recomended to have a source impedence of 100 or less for each input. The S/H circuit is optimized for a 50 source impedance. If the source impedance is less than 50, a series resistor should be added to increase this impedance to 50. The source impedence should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second.
VCM 4.7F 12pF 0.1F ANALOG INPUT 100 1:1 25 100 25 12pF 25 AIN+ 25 AIN
-
12pF
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Figure 3. Single-Ended to Differential Conversion Using a Transformer
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Input Drive Circuits Figure 3 shows the LTC1746 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedence seen by the ADC does not exceed 100 for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Figure 4 demonstrates the use of operational amplifiers to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. The 25 resistors and 12pF capacitors on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies higher than 50MHz, the capacitors may need to be decreased to prevent excessive signal loss.
VCM 5V SINGLE-ENDED INPUT 2.35V 1/2 RANGE 4.7F 12pF 25 25 A + IN LTC1746 12pF
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+
1/2 LT1810
-
LTC1746
100
+
1/2 LT1810
25
25 AIN- 12pF
-
500 500
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Figure 4. Differential Drive with Op Amps
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LTC1746
APPLICATIO S I FOR ATIO
Reference Operation
Figure 5 shows the LTC1746 reference circuitry consisting of a 2.35V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V(1V differential) or 3.2V(1.6V differential). Tying the SENSE pin to ground selects the 2V range; tying the SENSE pin to VDD selects the 3.2V range. The 2.35V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor of 4.7F or larger is required for the 2.35V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. This is also the compensation capacitor for the reference. It will not be stable without this capacitor.
LTC1746 2.35V VCM 4.7F 1.6V RANGE DETECT AND CONTROL SENSE REFLB 0.1F REFHA BUFFER INTERNAL ADC HIGH REFERENCE 1V 4 2.35V BANDGAP REFERENCE
TIE TO VDD FOR 3.2V RANGE; TIE TO GND FOR 2V RANGE; RANGE = 2 * VSENSE FOR 1V < VSENSE < 1.6V 1F
4.7F DIFF AMP 1F REFLA 0.1F REFHB INTERNAL ADC LOW REFERENCE
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Figure 5. Equivalent Reference Circuit
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The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins: REFHA and REFHB for the high reference and REFLA and REFLB for the low reference. The doubled output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 5. Other voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in Figure 6a. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device since the logic threshold is close to ground and VDD. The SENSE pin should be tied high or low as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1F ceramic capacitor.
2.35V VCM 4.7F 12.5k 1.1V 11k SENSE 1F LTC1746
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Figure 6a. 2.2V Range ADC
2.35V
VCM 4.7F
5V 0.1F
4
LT1790-1.25 1, 2
6
1.25V
SENSE 1F
LTC1746
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Figure 6b. 2.5V Range ADC with an External Reference
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LTC1746
APPLICATIO S I FOR ATIO
Input Range
The input range can be set based on the application. For oversampled signal processing in which the input frequency is low (<10MHz), the largest input range will provide the best signal-to-noise performance while maintaining excellent SFDR. For high input frequencies (>10MHz), the 2V range will have the best SFDR performance but the SNR will degrade by 3.5dB. See the Typical Performance Characteristics section.
ANALOG INPUT 0.1F CLOCK INPUT 50 1:4
ENC
ENC
Figure 7. Transformer Driven ENC/ENC with Equivalent Encode Input Circuit
VTHRESHOLD = 2V
ENC LTC1746
2V ENC 0.1F
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Figure 8a. Single-Ended ENC Drive, Not Recommended for Low Jitter
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Driving the Encode Inputs The noise performance of the LTC1746 can depend on the encode signal quality as much as on the analog input. The ENC/ENC inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 2V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits.
LTC1746 5V BIAS TO INTERNAL ADC CIRCUITS VDD 2V BIAS 6k VDD 2V BIAS 6k
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3.3V MC100LVELT22 3.3V 130 Q0 130 ENC LTC1746
D0
Q0 83
ENC 83
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Figure 8b. ENC Drive Using a CMOS-to-PECL Translator
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LTC1746
APPLICATIO S I FOR ATIO
Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies) take the following into consideration: 1. Differential drive should be used. 2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.8V to VDD. Each input may be driven from ground to VDD for single-ended drive. Maximum and Minimum Encode Rates The maximum encode rate for the LTC1746 is 25Msps. For the ADC to operate properly the encode signal should have a 50% (5%) duty cycle. Each half cycle must have at least 19ns for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty
VDD
DATA FROM LATCH OE
PREDRIVER LOGIC
Figure 9. Equivalent Circuit for a Digital Output Buffer
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cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. When using a single-ended encode signal asymmetric rise and fall times can result in duty cycles that are far from 50%. At sample rates slower than 25Msps the duty cycle can vary from 50% as long as each half cycle is at least 19ns. The lower limit of the LTC1746 sample rate is determined by the droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC1746 is 1Msps. DIGITAL OUTPUTS Digital Output Buffers Figure 9 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50 to external circuitry and may eliminate the need for external damping resistors.
LTC1746 VDD OVDD 0.5V TO VDD 0.1F OVDD 43 TYPICAL DATA OUTPUT OGND
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LTC1746
APPLICATIO S I FOR ATIO
Output Loading
As with all high speed/high resolution converters the digital output loading can affect the performance. The digital outputs of the LTC1746 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. A resistor in series with the output may be used but is not required since the ADC has a series resistor of 43 on chip. Lower OVDD voltages will also help reduce interference from the digital outputs. Format The LTC1746 parallel digital output can be selected for offset binary or 2's complement format. The format is selected with the MSBINV pin; high selects offset binary. Overflow Bit An overflow output bit indicates when the converter is overranged or underranged. When OF outputs a logic high the converter is either overranged or underranged. Output Clock The ADC has a delayed version of the ENC input available as a digital output, CLKOUT. The CLKOUT pin can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. Data will be updated just after CLKOUT falls and can be latched on the rising edge of CLKOUT.
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Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 3V supply then OVDD should be tied to that same 3V supply. OVDD can be powered with any voltage up to 5V. The logic outputs will swing between OGND and OVDD. Output Enable The outputs may be disabled with the output enable pin, OE. OE high disables all data outputs including OF and CLKOUT. The data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long periods of inactivity. GROUNDING AND BYPASSING The LTC1746 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane is recommended. The pinout of the LTC1746 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.
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LTC1746
APPLICATIO S I FOR ATIO
High quality ceramic bypass capacitors should be used at the VDD, VCM, REFHA, REFHB, REFLA and REFLB pins as shown in the block diagram on the front page of this data sheet. Bypass capacitors must be located as close to the pins as possible. Of particular importance are the capacitors between REFHA and REFLB and between REFHB and REFLA. These capacitors should be as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recomended. The large 4.7F capacitor between REFHA and REFLA can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC1746 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. An analog ground plane separate from the digital processing system ground should be used. All ADC ground pins labeled GND should connect to this plane. All ADC VDD bypass capacitors, reference bypass capacitors and input filter capacitors should connect to this analog plane. The LTC1746 has three output driver ground pins, labeled
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OGND (Pins 27, 38 and 47). These grounds should connect to the digital processing system ground. The output driver supply, OVDD should be connected to the digital processing system supply. OVDD bypass capacitors should bypass to the digital system ground. The digital processing system ground should be connected to the analog plane at ADC OGND (Pin 38). HEAT TRANSFER Most of the heat generated by the LTC1746 is transferred from the die through the package leads onto the printed circuit board. In particular, ground pins 12, 13, 36 and 37 are fused to the die attach pad. These pins have the lowest thermal resistance between the die and the outside environment. It is critical that all ground pins are connected to a ground plane of sufficient area. The layout of the evaluation circuit shown on the following pages has a low thermal resistance path to the internal ground plane by using multiple vias near the ground pins. A ground plane of this size results in a thermal resistance from the die to ambient of 35C/W. Smaller area ground planes or poorly connected ground pins will result in higher thermal resistance.
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LTC1746
PACKAGE DESCRIPTIO U
FW Package 48-Lead Plastic TSSOP (6.1mm)
(Reference LTC DWG # 05-08-1651)
12.4 - 12.6* (.488 - .496) 0.95 0.10 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 7.9 - 8.3 (.311 - .327) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1.20 (.0473) MAX 0 - 8 -C0.09 - 0.20 (.0035 - .008) 0.45 - 0.75 (.018 - .029) 0.50 (.0197) BSC 0.17 - 0.27 (.0067 - .0106) 0.05 - 0.15 (.002 - .006) -T.10 C
FW48 TSSOP 0502
8.1 0.10
6.2 0.10
0.32 0.05
0.50 TYP
RECOMMENDED SOLDER PAD LAYOUT 6.0 - 6.2** (.236 - .244)
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC1746 RELATED PARTS
PART NUMBER LT1019 LTC1196 LTC1405 LTC1406 LTC1410 LTC1411 LTC1412 LTC1414 LTC1415 LTC1419 LTC1420 LT1460 LTC1604/LTC1608 LTC1668 LTC1740 LTC1741 LTC1742 LTC1743 LTC1744 LTC1745 LTC1747 LTC1748 DESCRIPTION Precision Bandgap Reference 8-Bit, 1Msps Serial ADC 12-Bit, 5Msps, Sampling ADC 8-Bit, 20Msps ADC 12-Bit, 1.25Msps ADC 14-Bit, 2.5Msps ADC 12-Bit, 3Msps, Sampling ADC 14-Bit, 2.2Msps ADC Single 5V, 12-Bit, 1.25Msps 14-Bit, 800ksps ADC 12-Bit, 10Msps ADC Micropower Precision Series Reference 16-Bit, 333ksps/500ksps ADCs 16-Bit, 50Msps DAC 14-Bit, 6Msps ADC 12-Bit, 65Msps ADC 14-Bit, 65Msps ADC 12-Bit, 50Msps ADC 14-Bit, 50Msps ADC 12-Bit, 25Msps ADC 12-Bit, 80Msps ADC 14-Bit, 80Msps ADC COMMENTS 0.05% Max Initial Accuracy, 5ppm/C Max Drift 3V to 5V, SO-8 5V or 5V Pin Compatible with the LTC1420 Undersampling Capability Up to 70MHz Input 5V, 71dB SINAD 5V, No Pipeline Delay, 80dB SINAD 5V, No Pipeline Delay, 72dB SINAD 5V, 81dB SINAD and 95dB SFDR 55mW Power Dissipation, 72dB SINAD 5V, 95dB SFDR 71dB SINAD and 83dB SFDR at Nyquist 0.075% Accuracy, 10ppm/C Drift 16-Bit, No Missing Codes, 90dB SINAD, -100dB THD 87dB SFDR at 1MHz fOUT, Low Power, Low Cost Low Power, 79dB SINAD, 91dB SFDR Pin Compatible with the LTC1746 Pin Compatible with the LTC1746 Pin Compatible with the LTC1746 Pin Compatible with the LTC1746 Pin Compatible with the LTC1746 Pin Compatible with the LTC1746 Pin Compatible with the LTC1746
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
LT/TP 0903 1K * PRINTED IN THE USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2003

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